The present invention generally relates to memory devices employing address multiplexing, and more particularly to a memory device employing address multiplexing and comprising a counter which generates an address of a column decoder responsive to toggle of a column address strobe (CAS).
As modes of writing and reading data from a memory device at a high speed, there are the page mode and the nibble mode. In a memory device employing the address multiplexing, column and row addresses are received from an exterior responsive to a row address strobe (RAS) and a column address strobe (CAS), respectively. The timings of the RAS and the CAS are used effectively in the page and nibble modes to realize the high-speed operation.
In the page mode, a plurality of inverted column address strobes (hereinafter simply referred to as CAS) are entered for one active time period of an inverted row address strobe (hereinafter simply referred to as a RAS), so that the writing and reading of data to memory cells can be carried out at a high speed. In other words, access is made to the memory cells designated by a row address which is set when the RAS is made active, by successively entering a column address and the CAS in a state where the RAS is maintained active. Since the access is made to the memory cells without changing the row address, there is no address selection time nor resetting time for the row selection, and it is thus possible to obtain a quick access time and a short cycle time. In addition, in the case of a 64 K memory device, for example, it is possible to make access to the memory cells corresponding to 256 bits during one active time period of the RAS, and it is possible to carry out the writing and reading of data to and from these memory cells at random.
On the other hand, in the nibble mode, it is only possible to make access to the memory cells corresponding to 4 bits during one active time period of the RAS. However, when making access to the 4 bits, it is only necessary to initially determine the first bit by an external address, and the access to the remaining bits can be made serially and cyclicly thereafter by merely entering the CAS. Accordingly, unlike in the page mode, there is no need to enter the column address in correspondence with each CAS, and it is hence possible to carry out the writing and reading of the data at an even higher speed compared to the page mode.
But as will be described later on in conjunction with drawings, there are problems in that the numbers of data bus pairs, sense and latch circuits, and write-in buffers become extremely large for a large number of parallel input and output bits, and these data buses and circuit parts occupy a large area of the memory device. In addition, there is a problem in that the power consumption becomes large due to the large number of circuit parts. On the other hand, similar problems occur when the number of serial bits to be outputted in the nibble mode becomes large.